1. The Field of the Invention
Embodiments of the present invention relate generally to methods for forming a gate electrode of a semiconductor device.
2. The Relevant Technology
A MOS (Metal-Oxide Semiconductor) transistor is one example of a semiconductor device. The MOS transistor includes a source region and a drain region, which are spaced from each other by a predetermined distance. A channel region is defined in a predetermined portion of the semiconductor substrate substantially between the source and drain region, and a gate electrode is stacked on top of the channel region. Typically, a gate dielectric film, such as a gate oxide film is disposed between the gate electrode and the channel region. Usually the source region and drain region, the gate oxide film, and the gate electrode are all covered with an interlayer dielectric film.
In this type of configuration, the channel region, the gate oxide film, and the gate electrode constitute one capacitor, and an inversion layer or an accumulation layer is formed in the channel region according to a voltage applied to the gate electrode. Accordingly, the gate electrode functions to control current flowing between the source drain and the drain region.
Optimally, the gate electrode has good conductivity, has a high melting point, and is easy to pattern. To achieve these conditions, the gate electrode is typically formed of a polysilicon film, which is easily doped with impurities at a high concentration and can be kept in a stable shape in a subsequent thermal process that is conducted at a high temperature.
FIGS. 1a to 1d are cross sectional views sequentially illustrating a conventional process for forming a gate electrode.
In this process, a gate electrode 30′ is formed by a combination of a typical photo-lithography process and a subsequent etching process.
For example, as is shown in FIG. 1, a gate oxide film 20 is formed on the entire surface of a semiconductor substrate 10 by a method, such as deposition, and then a polysilicon film 30 for a gate electrode 30 is formed to be stacked on the entire surface of the corresponding gate oxide film 20 by a method, such as deposition.
For the deposition of the gate oxide film 20 and the polysilicon film 30, an LPCVD (Low Pressure Chemical Vapor Deposition) can be used.
Afterwards, as shown in FIG. 1b, a photoresist pattern 40 is formed on top of the corresponding polysilicon film 30 by a typical photo-lithography process so as to enclose and define only the region in which a gate electrode 30′ (FIG. 1c) is to be formed. The photo-lithography process includes a series of steps, such as photoresist solution coating, exposure, and development steps.
Next, as shown in FIG. 1c, portions of the polysilicon film 30 and gate oxide film 20 except for the region where the photoresist pattern 40 is formed are selectively removed by etching by using the formed photoresist pattern 40 as an etching mask. A gate electrode 30′ is formed by way of the remaining polysilicon film 30 material.
The etching may be a dry etching having an anisotropic characteristic, such as RIE (Reactive Ion Etching).
As is shown in FIG. 1d, the photoresist pattern 40 is then removed by, for example, a plasma ashing process.
When necessary, a BARC (Bottom of Anti-Reflection Coating) film can be formed under the photoresist pattern 40 so as to prevent the reflection of an exposure light upon exposure during the photo-lithography process. In this case, the BARC film is removed first upon etching, and then the polysilicon film 30 and the gate oxide film 20 are removed under other process conditions.
The gate electrode 30′ exerts a large effect on the characteristics of the semiconductor device. In particular, the line width of the gate electrode 30′ can become ultra fine.
In order to form a fine gate electrode 30′, first, the photoresist pattern 40 should be formed to be fine. To do so, there have been attempts to implement the photoresist pattern 40 having a fine line width by using short-wavelength light sources, such as a KrF having a 248 nm wavelength or an ArF having a 193 nm wavelength as a light source upon exposure and using a photoresist film of the type capable of optically reacting to these light sources. However, this approach is not without drawbacks. In particular, an exposure apparatus having a short-wavelength light source is expensive, which results in higher overall manufacturing costs.
In one conventional approach, the line width is made smaller by etching the edges of the photoresist pattern 40 formed by the photo-lithography process by additionally performing a photoresist trimming process. However, this solution is not entirely satisfactory either since the vertical thickness of the photoresist pattern 40 is reduced by trimming etching, the corresponding photoresist pattern 40 cannot resist the subsequent polysilicon film 30 in a main etching stage, which can cause an etching deficiency.